Free Webinar – Mixed-Signal Verification with UVM

Become Silicon Synergy Certified

Length of the Webinar: 3 Days (8 Hours Per Day)

Course Description

In this course, you learn Mixed-Signal verification with UVM. The Accellera standard Universal Verification Methodology – Mixed Signal (UVM-MS) architecture is used to develop a mixed-signal testbench and verify the Mixed-Signal Design Under Test (MS-DUT). You get to analyze different components inside the UVM-MS testbench and different aspects of analog mixed-signal communication.

For this course, you use the command-line-based Xcelium™ Use model that uses the xrun executable to run the simulations.

You are also introduced to the Cadence® Mixed-Signal IP and SOC Verification Solution and Mixed-Signal Metric Driven(MS-MDV) methodology.

Learning Objectives

After completing this course, you will be able to:

1. Set up and run UVM-MS testbench to verify mixed-signal design
2. Analyze the different verification components (UVCs), and AMS and DMS communication
3. Use the randomization approach for precise verification of analog blocks
4. Perform assertion-based checks on analog signals
5. Perform SPICE metric driven block level verification with the Verisium™ Manager

Softwares Used in This Course

1. XA310 Xcelium Digital Mixed Signal App
2. 70060 Spectre AMS Connector
3. 90006 Spectre/Multi Mode Tokens
4. X300 Xcelium Single Core
5. 29010 SimVision Mixed-Signal Debug Option
6. VERMGR Verisium Manager

Modules in this Course

1. Introduction to UVM-MS
2. UVM-MS Components
3. Analog Resource Communication
4. UVM-MS Additional Features
5. Adapting MDV to Mixed-Signal Designs
6. Appendices: UVM Basics and SystemVerilog Real Number Modeling Examples

Audience

1. Analog/Mixed-Signal IC Designers
2. Analog/Mixed-Signal Verification Engineers
3. Digital Verification Engineers

Prerequisites

Before taking this course, you need to have:
1. A good working knowledge of SystemVerilog and UVM

Or you must have completed our following courses:
2. SystemVerilog Accelerated Verification with UVM
3. Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
4. Behavioral Modeling with Verilog-AMS
5. Real Modeling with SystemVerilog

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Related Courses – Coming Soon

The following are related courses to Mixed-Signal Verification.

1. Mixed Signal Simulations Using Spectre AMS Designer
2. SimVision for Debugging Mixed-Signal Simulations
3. Real Modeling with Verilog-AMS
4. Analog Modeling with Verilog-A