Real Number Modeling with System Verilog – Course Duration Real Number Modeling – 3 Days (8 hours per Day) Real Number Modeling with System Verilog – Abstracts Nowadays, the semiconductor industry directs its attention to mixed-signal System-on-Chip (SoC) applications. Main targets are the creation of accurate and fast mixed-signal SoC designs, composed of both digital…
Length of the Webinar: 3 Days (8 Hours Per Day) Course Description In this course, you use the Virtuoso® ADE Explorer and Spectre® Circuit Simulator/Spectre Accelerated Parallel Simulator (APS) to simulate analog circuits with Verilog-A models. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their…
Become Silicon Synergy Certified Length of the Webinar: 3 Days (8 Hours Per Day) Course Description In this course, you learn Mixed-Signal verification with UVM. The Accellera standard Universal Verification Methodology – Mixed Signal (UVM-MS) architecture is used to develop a mixed-signal testbench and verify the Mixed-Signal Design Under Test (MS-DUT). You get to analyze…
Enroll Today for Free Conference or Webinar on Mixed Signal Design It’s our mission to inform and stimulate how-to discussions on the hottest topics in our training catalog. Training and Webinars are delivered live by subject matter experts either on-line or visiting your colleges. At the end of each Training/Webinar, we host an open Q&A…
