Analog IC Design
1. Analog IC & Circuit Design
Analog IC & Circuit Design Course primarily designed to cover very important basics of Analog Integrated Circuit design. This course covers all the way from basic MOSFET modelling to complex analog block designs. Mainly focused on giving hands-on practical exposure in doing circuit design for a given analog & mixed signal product. By end of the course you will learn circuit design using industry standard EDA tool, simulation, design verification of typical analog circuits such as Op-Amps, PLL, Bandgap reference, LDO’s including basics of PLL, ADC’s and DAC’s.
Eligibility
4 Years B.E/B.Tech in Electricals or Electronics Engineering or M.E/M.Tech/M.S in VLSI System Design/Embedded Systems/Digital Electronics.
Duration of the Course/Training
6 Months
Features Highlights of Analog IC Design
1. Deep understating MOSFETs W.r.t Modelling, Noise, Matching & Non- Linearity
2. Understand Analog Circuit Basics of Single Stage Amps, Differential Amps, Current Mirrors, Two Stage Opamp Design, Feedback Theory & Frequency Compensation
3. Understand Critical Analog Blocks such as Band Gap reference Design, Oscillators, Phase Lock Loop Designs
4. Critical Industry standard project execution under the guidance of 15+ year’s industry expert.
5. 24×7 Lab Support with classroom practice handouts and course material.
6. Soft skills development, job oriented analog design training with 100% placement assistance.
Course Description
Primarily this course is designed to cover very important basics of Analog Integrated Circuit design. This course covers all the way from MOSFET modelling to Complex Analog Block designs. Mainly focused on giving hands-on practical exposure in doing circuit design for a given analog & mixed signal product. By end of the course you will learn circuit design in EDA tool, simulation, design verification of typical analog circuits such as Op-Amp, PLL, Bandgap, LDO. Course also focus on giving insights of the design and simulation of I/O’s, Memory as well. After completing the course, you will get opportunity to move into domains such as Analog & Mixed Signal Design, Memory Design, Standard Cell Design, and I/O Design.
Course Curriculum
| SL Number | Module Number | Module Name | Lesson Number | Lesson Name |
|---|---|---|---|---|
| 1 | M1 | Fundamentals of Microelectronics | ||
| 1.1 | 1 | Semiconductor Device Physics | ||
| 1.2 | 2 | Semiconductor Basics and CMOS Process | ||
| 1.3 | 3 | MOSFET, BJT & Diode Basics, Small Signal and Large Signal Models | ||
| 1.4 | 4 | Regions of operation of MOSFET - capacitor based (accumulative, depletion, inversion) and conduction based (saturation, cutoff, linear) | ||
| 1.5 | 5 | Short Channel Effects of MOSFET | ||
| 2 | M2 | Linux & EDA Tools Introduction | ||
| 2.1 | 1 | Linux introduction | ||
| 2.2 | 2 | Cadence tool introduction | ||
| 2.3 | 3 | Schematic creation+simulation (dc, tran, ac) | ||
| 2.4 | 4 | Simulation requirements, types | ||
| 2.5 | L1 |  | 5 | Lab1: MOSFET Characterization |
| 3 | M3 | Single Stage Amplifiers | ||
| 3.1 | 1 | Intro to single stage amplifiers | ||
| 3.2 | 2 | Common Source (resistor, mos load), Common Gate & Source Follower Designs | ||
| 3.3 | 3 | Cascode Stages Design (CS+CG), benefits | ||
| 3.4 | 4 | Common source with source degeneration | ||
| 3.5 | 5 | Impedence of single mosfet, Rout of amplifiers | ||
| 3.6 | L2 | | 6 | Lab2: On Single stage amplifiers |
| 4 | M4 | Current Mirror | ||
| 4.1 | 1 | Current reference/source basics | ||
| 4.2 | 2 | Current Mirror basics - simple current mirror | ||
| 4.3 | 3 | Current mirror - cascode | ||
| 4.4 | 4 | Accurate current mirrors, better matching techniques, Low voltage current mirror | ||
| 4.5 | L3 | | 5 | Lab3: Current mirror improving accuracy |
| 5 | M5 | Differential Amplifiers | ||
| 5.1 | 1 | Differential amplifier - why? | ||
| 5.2 | 2 | Single Ended Vs Differential Design | ||
| 5.3 | 3 | Specifications of differential amplifier | ||
| 5.4 | 4 | Functioning of diff amp, analysis | ||
| 5.5 | 5 | Current mirror loading (5T OTA) | ||
| 5.6 | 6 | Gain, CMRR, slew rate of 5T OTA | ||
| 5.7 | 7 | Intro to pole, zeros in circuits | ||
| 5.8 | 8 | Design of 5T OTA, 9T OTA | ||
| 6 | M6 | Feedback & Stability | ||
| 6.1 | 1 | Need for feedback | ||
| 6.2 | 2 | Different types of feedback | ||
| 6.3 | 3 | Basics of bode plots, stability criteria | ||
| 6.4 | 4 | Miller compensation, compensation types and need | ||
| 6.5 | 5 | Terms: Unity gain bandwidth, DC gain, Phase margin, Gain margin | ||
| 7 | M7 | Operational Amplifiers Design | ||
| 7.1 | 1 | Two stage opamp as LDO/regulator | ||
| 7.2 | 2 | Concepts of regulator stability | ||
| 7.3 | 3 | PMOS driver vs NMOS driver, Cap load vs current load - stability scenarios | ||
| 7.4 | 4 | Miller compensaton, bode plots for regulator | ||
| 7.5 | L4 | | 5 | Lab4: Design of a voltage regulator |
| 8 | M8 | Voltage Regulators Design | ||
| 8.1 | 1 | Two stage opamp as LDO/regulator | ||
| 8.2 | 2 | Concepts of regulator stability | ||
| 8.3 | 3 | PMOS driver vs NMOS driver, Cap load vs current load - stability scenarios | ||
| 8.4 | 4 | Miller compensaton, bode plots for regulator | ||
| 8.5 | L5 | | 5 | Lab5: Design of a voltage regulator |
| 9 | M9 | Reference Circuits | ||
| 9.1 | 1 | Basics of Bandgap reference | ||
| 9.2 | 2 | Design of conventional bandgap reference circuit, need for startup | ||
| 9.3 | 3 | constant-gm circuit for current bias generation | ||
| 9.4 | 4 | sub 1-V BGR design concepts | ||
| 9.5 | 5 | Current reference circuits | ||
| 9.6 | L6 | | 6 | Lab6: Design of conventional bandgap reference circuit |
| 10 | M10 | Oscillators | ||
| 10.1 | 1 | Basics of oscillators, feedback concepts | ||
| 10.2 | 2 | Types of oscillators - feedback and relaxation | ||
| 10.3 | 3 | Oscillator design - feedback based (Ring, LC, VCO) | ||
| 10.4 | 4 | Relaxation oscillator - building a circuit from scratch (RC and IC based oscillators) | ||
| 10.5 | 5 | Problems in relaxation oscillator design | ||
| 10.6 | L7 | | 6 | Lab7: Design of IC oscillator |
| 11 | M11 | PLL | ||
| 11.1 | 1 | PLL need - theory | ||
| 11.2 | 2 | PLL concepts, building blocks | ||
| 11.3 | 3 | PLL block details, VCO in detail | ||
| 11.4 | 4 | Types of PLL - Pros and Cons | ||
| 12 | M12 | Data Converters | ||
| 12.1 | 1 | DACS concept/specs, usage | ||
| 12.2 | 2 | ADC basics and concepts/specs, types of ADC | ||
| 12.3 | 3 | Details of flash ADC, slope based ADC, | ||
| 12.4 | 4 | SAR ADC, Pipeline ADC, Sigma-delta ADC | ||
| 12.5 | L8 | | 5 | Lab8: Design of 4 bit ADC |
| 13 | M13 | Important Misc Concepts | ||
| 13.1 | 1 | Analog self-testing circuits | ||
| 13.2 | 2 | Concepts of trimming | ||
| 13.3 | 3 | Layout basics, common centroid, shielding etc | ||
| 13.4 | 4 | Testing analog circuits - bulding testable circuits | ||
| 14 | M14 | Final Project Work | ||
| 14.1 | 1 | This includes Design of the Project and Lab. Students has to share the report with the working design as per spec | ||
| 15 | M15 | DFT (Analog Fault Simulation) | ||
| 15.1 | 1 | Analog Fault Simulation | ||
| 16 | M16 | Introduction to Mixed Signal Design | ||
| 16.1 | 1 | Introduction to Mixed Signal Design |
EDA Tools & & Technology Used for Analog IC Design Course
- EDA Tools: Synopsys VCS Suite & Cadence Xcelium.
- Technology Used: 14nm FINFET & 28nm Planar MOSFET.
- Lab Access: Flexible learning with 24×7 online access to all the EDA tools that are running on high speed cloud servers in USA.
- Access EDA tools, designs and libraries anytime and anywhere in the globe through VPN.
Course Duration and Timings
- 24 weeks/6 Months on Saturday and Sunday
- 3 Hours of live lecture session on Saturday and Sunday
- 1 Hours of live online lab session with EDA tools.
- Access help on weekdays too.
Flexible and Affordable Course Payments
- Pay through Debit/Credit Cards or Net Banking or through UPI payments.
- Avail No-cost EMI option with zero processing fee from our financial partners.
- You can choose 3 to 12 months of flexible EMI terms without paying any interest on your loan during your courses. Start making the payments once the placement is done.
- Group (3 or more enrollment together) and deep discounts for Engineering colleges
Placement Assistance after the Completion of Analog IC Design Course
Our placements consultants works closely with the leading VLSI companies to meet their entry and mid level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The hiring companies include both India and USA companies.
We provide placement support as complementary service until the trained engineers gets job. For more information, please speak to our placement counsellors.
About Instructors
VLSI and Analog IC Design Professional with 35+ and 15+ years of rich experience in Analog & Mixed-Signal Circuit designs. Worked with major semiconductor product and service companies including EDA companies in India, Japan and USA and also 10 years of system design experiences in startup companies for the industrial automation products, which helped our instructors to understand the learning curves and business models. Having facilitative leadership skills and having a proven track record with leading teams on-site & offshore design centers including to create Analog & Mixed-Signal course materials and as instructor.
Why Choose Silicon Synergy
Trained Students Reviews
Deepak Sharma – Analog IC Designer at Micron:
Intensive training for verification course. Got placed in Radiant Semiconductors, with good efforts from placement team who are really hard working. Daily and weekend training is good to understand complete SV and UVM with real time projects. If you want to develop good verification skill I would suggest Silicon Synergy as the best training place.
Rajesh Rao – Layout Designer at Cadence:
I got to know about the school through Silicon Synergy career awareness program. I always had an interest in VLSI but don’t know how to pick the best career for myself. Through their career awareness program, I was given all the information I needed to know. I am now fully enrolled with the institute and got placed in Cadence as Physical Design Engineer.
Kiran Bhat – VLSI Verification Engineer at Intel:
It was fun been a part of the Institute. I had so many wonderful experiences during my time in Silicon Synergy. So far I don’t think there is anywhere you can get such quality of trainers they have at Silicon Synergy. They are very friendly and take work at the student’s pace to ensure everyone is carried along. It was an amazing time at the Silicon Synergy and I am very grateful.
Enroll Now into this Course
FAQ
1: How Online VLSI Courses will be delivered and what are the timings ?
Answer: Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login to the Silicon Synergy e-learning portal. For Lab access, you will connect to the Silicon Synergy servers through a VPN between 9:30 am to 1 pm, Saturday and Sundays. These timings are in IST (Indian Standard Timing) time zone.
Session Details: 9.30 am to 11.00 am
Lecture Sessions: 11.00 am to 11.30 am
Session Break: 11.30 am to 01.00 pm
Lab Session: The course will be delivered by one of the retired senior VP who have 35 years of VLSI experience along with 15+ years of experienced VLSI Engineer. Both are currently working in VLSI industry on latest technologies.
2: May I know about the trainers experience details ?
Answer: Our trainers are typically having 15 to 30 years of VLSI industry experience from USA, Japan and India and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills. They are available on weekends only, during class hours for live interaction.
3: Who can Join Silicon Synergy’s Online VLSI Courses?
Answer: Instructor-led online courses on weekends are primarily designed for working professionals and Freshers who want to skill or upskill themselves. With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity. Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses. Considering time constraints for all working professionals, you can attend these courses from home.
4: What Tools & Technologies are used in the Online Courses?
Answer: We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 14nm libraries are used for labs, projects. Synopsys and Cadence tools are used by the majority of the IC Design companies in the semiconductor(VLSI) industry world wide, not just in India.
5: How Can I Access the Labs/Tools remotely ?
Answer: Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.
6: How Long Can I get VPN access to the Lab, after completion of the course ?
Answer: It varies as per the course duration (short/long). please check the Lab tab, in your course pages. Our course counselors can help you as well.
7: Do You have EMI/Installment option available?
Answer: We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs. please check with our Course Counsellors.
8: Do you provide Certificate after completion of the course ?
Answer: Course completion certificates will be provided, whoever meets the course completion criteria.
9: Do you provide Placement assistance ?
Answer: Silicon Synergy provides placement help to all candidates by providing them industry interview opportunities.
10: How long can I have lab access after course completion?
Answer: You will have lab access until the placement is done + 2 weeks after the placement.
