Digital IC Design and Verification
Digital IC Design and Verification
Digital IC Design and Verification course is designed by 35+ years experienced US industry experts, mainly for fresh engineering graduates and professionals to meet the current and future demands of the semiconductor industry. Our course offers comprehensive RTL Design & Verification Training in Bangalore. RTL design is a crucial step in the chip design process.
Eligibility
4 Years B.E/B.Tech in Electricals or Electronics Engineering or M.E/M.Tech/M.S in VLSI System Design/Embedded Systems/Digital Electronics.
Duration of the Course/Training
6 Months
Course Description
Mainly focused on enhancing the Design Verification skills needed by industry. The curriculum is designed to include the latest methodologies being adopted by industry. By end of the course you will have hands on experience in design and verification with Verilog, system Verilog (SV) in UVM methodology.
Digital IC Design and Verification Course Features and Highlights
1. Understanding on ASIC/FPGA Design Flows.
2. Deep understanding of Advanced Digital Logic concepts and Designs Verification skills.
3. Strong hands on System Verilog and UVM for Design Verification.
4. Developing the Verification Plan, Functional Coverage closure, SVAs etc.
5. Regression flow automation.
6. 24×7 Lab Support with Lab practice handouts and course material delivery.
7. Industry standard project execution, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
8. Soft skills development, complete suite of job oriented ASIC Verification training with 100% placement assistance.
9. Verilog, RTL Design, RTL Verification Training Institute
Digital IC Design and Verification Course Curriculum
SL Number | Module Number | Module Name | Lesson Number | Lesson Name |
---|---|---|---|---|
1 | M1 | Introduction to Linux and EDA Tools | ||
1.1 | 1 | Components of the UNIX/Linux System | ||
1.2 | 2 | Utilities and COmmands | ||
1.3 | 3 | VI and VIM Editors | ||
1.4 | 4 | Basics of Shell Scripting | ||
1.4 | L1 | 5 | Lab1: | |
2 | M2 | Digital Design | ||
2.1 | 1 | Introduction to Digital Design(Analog & Digital Signals, why digital signal, Design Process, Limitations) | ||
2.2 | 2 | Number Systems(Introduction,Conversion from one number system to another,Signed & Unsigned Binary numbers,Binary Arithmetic) | ||
2.3 | 3 | Binary Codes(Introduction,BCD Code, Excess-3 Code,Gray code,Alphanumeric code,Error detection and correction codes) | ||
2.4 | 4 | Introduction to Boolean Algebra(Introduction,Axioms of Boolean Algebra, Logic gates) | ||
5 | Gate level Optimization(Introduction,K map, Optimization using K Map,OR-AND,AND-OR,AOI Implementation) | |||
6 | Sequential Circuits - Design and Analysis(Introduction,Difference between combinational and Sequential Circuits,Types of Triggering,Latches and Flip flops,Registers,Counters,Synchronous Counters,Asynchronous Counters ) | |||
7 | Memories(Introduction, Random Access Memory, ROM, SRAM, DRAM and PLD) | |||
8 | Finite State Machine - Mealy & Moore FSM | |||
9 | Data Converters: Sample and Hold Circuits, ADCs and DACs | |||
2.5 | L2 | 5 | Lab2: | |
3 | M3 | Introduction to VLSI | ||
3.1 | 1 | Introduction to VLSI | ||
3.2 | 2 | VLSI Design Flow | ||
3.3 | 3 | ASIC vs FPGA | ||
3.4 | 4 | RTL Design Methodologies | ||
3.5 | 5 | Introduction to ASIC Verification Methodologies | ||
4.4 | 6 | VLSI Design Flow Steps - Demo | ||
4 | M4 | Verilog Language Introduction | ||
4.1 | 1 | Verilog Language Basics | ||
4.2 | 2 | Verilog Simulation using Cadence Tools | ||
4.3 | 3 | Verilog Constructs | ||
5 | M5 | Verilog Design and Verification Projects | ||
5.1 | 1 | DFF Coding using gate level, behavioral. structural | ||
5.2 | 2 | Adder | ||
5.3 | 3 | Counters | ||
5.4 | 4 | Memory RTL Coding and TB Developments | ||
5.5 | 5 | FIFO | ||
5.6 | 6 | Finite State Machines | ||
5.7 | 7 | Patteren Detector | ||
5.8 | 8 | Traffic Loght Controller Project | ||
5.9 | 9 | APB Protocol | ||
5.10 | 10 | Interupt Controller | ||
5.11 | 11 | SPI Controller | ||
5.12 | 12 | CRC generation | ||
6 | M6 | System Verilog (SV) Language Introduction | ||
6.1 | 1 | Functional Verification Overview | ||
6.2 | 2 | System Verilog Course Overview | ||
6.3 | 3 | Operators, Data Types | ||
6.4 | 4 | Arrays | ||
6.5 | 5 | Object Oriented Programming | ||
6.6 | 6 | Advanced Data types | ||
6.7 | 7 | Fork join, Inter process synchronization | ||
6.8 | 8 | Project to learn all SV language constructs | ||
6.9 | 9 | Program | ||
6.10 | 10 | Scheduling semantics | ||
6.11 | 11 | Task, Function | ||
6.12 | 12 | Constraints, Randomization | ||
6.13 | 13 | Functional and code coverage | ||
6.14 | 14 | Assertions and Assertion based verification | ||
6.15 | 15 | DPI | ||
6.16 | 16 | Configuration libraries, Packages, XMR | ||
6.17 | 17 | Configuration libraries, Packages, XMR | ||
7 | M7 | UVM | ||
7.1 | 1 | Introduction to UVM | ||
7.2 | 2 | UVM Phases | ||
7.3 | 3 | Transaction Level Modeling | ||
7.4 | 4 | Factory Registration & Methods | ||
7.5 | 5 | Universal Verification Concepts | ||
7.6 | 6 | RAL | ||
7.7 | 7 | Advanced concepts in UVM | ||
8 | M8 | AXI Protocol & AXI VIP & TB Development | ||
9 | M9 | ASIC Verification Concepts | ||
10 | M10 | Ethernet, MAC Core Functional Verification using SV & UVM | ||
11 | M11 | RTL Debug Concepts | ||
12 | M12 | SoC Verification Concepts | ||
13 | M13 | ASIC Flow | ||
14 | M14 | Perl or Python Scripting Introduction | ||
1 | Python Interpreter | |||
2 | Variables | |||
3 | File Management | |||
4 | Subroutines | |||
5 | Regular Expressions | |||
6 | OBject Orianted Python | |||
7 | Python Modules | |||
8 | Python Program Execuation with Small Project | |||
15 | M15 | Job Assitance and Soft Skill Training | ||
1 | Preparing for Interview, Resume Help. Mock Interviews etc | |||
2 | Facing Interview Effectively | |||
3 | Industry Work Culture | |||
4 | Group/Technical Discussions | |||
5 | Placement Help and Training Continuation with us Until the Job is Placed. | |||
16 | M16 | Final Course Assignments/Projects | ||
1 | 100+ detailed assignments covering all aspects of Verilog, System Verilog UVM, AXI Protocol, VIP Development, Advanced Digital Design, RTL Debug, Ethernet and MAC Core Verification, UNIX/Linux, PERL/Python and SHELL Scripting |
EDA Tools & Technology Used for Digital IC Design and Verification Course
- EDA Tools: Synopsys VCS Suite & Cadence Xcelium.
- Technology Used: 14nm FINFET & 28nm Planar MOSFET.
- Lab Access: Flexible learning with 24×7 online access to all the EDA tools that are running on high speed cloud servers in USA.
- Access EDA tools, designs and libraries anytime and anywhere in the globe through VPN.
Digital IC Design and Verification Course Duration and Timings
- 24 weeks/6 Months on Saturday and Sunday
- 3 Hours of live lecture session on Saturday and Sunday
- 1 Hours of live online lab session with EDA tools.
- Access help on weekdays too.
Flexible and Affordable Course Payments
- Pay through Debit/Credit Cards or Net Banking or through UPI payments.
- Avail No-cost EMI option with zero processing fee from our financial partners.
- You can choose 3 to 12 months of flexible EMI terms without paying any interest on your loan during your courses. Start making the payments once the placement is done.
- Group (3 or more enrollment together) and deep discounts for Engineering colleges
Placement Assistance & Guaranteed Placements after the Digital IC Design and Verification Course
Our placements consultants works closely with the leading VLSI companies to meet their entry and mid level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The hiring companies include both India and USA companies.
We provide placement support as complementary service until the trained engineers gets job. For more information, please speak to our placement counsellors.
About Course Instructors
VLSI, Digital, ASIC and Analog IC Design Professional with 35+ and 15+ years of rich experience in Digital, Analog & Mixed-Signal Circuit designs and Verifications. Worked with major semiconductor product and service companies including EDA companies in India, Japan and USA and also 10 years of system design experiences in startup companies for the industrial automation products, which helped our instructors to understand the learning curves and business models. Having facilitative leadership skills and having a proven track record with leading teams on-site and offshore design centers including to create Analog & Mixed-Signal course materials and as instructor.
Why Choose Silicon Synergy for Digital IC Design and Verification Course
Trained Students Reviews
Deepak Sharma – Analog IC Designer at Micron:
Intensive training for verification course. Got placed in Radiant Semiconductors, with good efforts from placement team who are really hard working. Daily and weekend training is good to understand complete SV and UVM with real time projects. If you want to develop good verification skill I would suggest Silicon Synergy as the best training place.
Rajesh Rao – Layout Designer at Cadence:
I got to know about the school through Silicon Synergy career awareness program. I always had an interest in VLSI but don’t know how to pick the best career for myself. Through their career awareness program, I was given all the information I needed to know. I am now fully enrolled with the institute and got placed in Cadence as Physical Design Engineer.
Kiran Bhat – VLSI Verification Engineer at Intel:
It was fun been a part of the Institute. I had so many wonderful experiences during my time in Silicon Synergy. So far I don’t think there is anywhere you can get such quality of trainers they have at Silicon Synergy. They are very friendly and take work at the student’s pace to ensure everyone is carried along. It was an amazing time at the Silicon Synergy and I am very grateful.
Enroll Now into Digital IC Design and Verification Course
FAQ
1: How Online VLSI Courses will be delivered and what are the timings ?
Answer: Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login to the Silicon Synergy e-learning portal. For Lab access, you will connect to the Silicon Synergy servers through a VPN between 9:30 am to 1 pm, Saturday and Sundays. These timings are in IST (Indian Standard Timing) time zone.
Session Details: 9.30 am to 11.00 am
Lecture Sessions: 11.00 am to 11.30 am
Session Break: 11.30 am to 01.00 pm
Lab Session: The course will be delivered by one of the retired senior VP who have 35 years of VLSI experience along with 15+ years of experienced VLSI Engineer. Both are currently working in VLSI industry on latest technologies.
2: May I know about the trainers experience details ?
Answer: Our trainers are typically having 15 to 30 years of VLSI industry experience from USA, Japan and India and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills. They are available on weekends only, during class hours for live interaction.
3: Who can Join Silicon Synergy’s Online VLSI Courses?
Answer: Instructor-led online courses on weekends are primarily designed for working professionals and Freshers who want to skill or upskill themselves. With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity. Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses. Considering time constraints for all working professionals, you can attend these courses from home.
4: What Tools & Technologies are used in the Online Courses?
Answer: We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 14nm libraries are used for labs, projects. Synopsys and Cadence tools are used by the majority of the IC Design companies in the semiconductor(VLSI) industry world wide, not just in India.
5: How Can I Access the Labs/Tools remotely ?
Answer: Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.
6: How Long Can I get VPN access to the Lab, after completion of the course ?
Answer: It varies as per the course duration (short/long). please check the Lab tab, in your course pages. Our course counselors can help you as well.
7: Do You have EMI/Installment option available?
Answer: We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs. please check with our Course Counsellors.
8: Do you provide Certificate after completion of the course ?
Answer: Course completion certificates will be provided, whoever meets the course completion criteria.
9: Do you provide Placement assistance ?
Answer: Silicon Synergy provides placement help to all candidates by providing them industry interview opportunities.
10: How long can I have lab access after course completion?
Answer: You will have lab access until the placement is done + 2 weeks after the placement.