VLSI Physical Design Flow

The chip design includes different types of processing steps to finish the entire flow. For anyone, who just started his career in VLSI physical design domain has to understand all the steps of the VLSI physical design flow. Each and every step of the VLSI physical design flow has a dedicated EDA tool that covers all the aspects related to the specific task perfectly. All the EDA tools can import and export the different file types to help making a flexible VLSI design flow that uses multiple tools from different vendors.

Physical design is process of transforming netlist into layout [GDSII]. Main steps in physical design are floorplanning, placement of all logical cells, clock tree synthesis & routing. During this process of physical design area, timing, power, design & technology constraints have to be met. Further design might require being optimized with respect to area, power, timing and performance. The VLSI physical design flow is shown in the figure below.

Here is a brief description of each step in VLSI Physical Design Flow:

Import Design or Netlist-In

• Import design or netlist-In is first step in physical design flow.
• In this step we import all design files and constraints files such as netlist, sdc, upf, def, technology file, logical and physical libraries and tlu+ file.

Floorplanning or chip planning

• This is the major step in physical design flow. In this step we have netlist which describes the design and the various blocks of the design and the interconnection between the different blocks. The netlist is the logical description of the ASIC design. Floorplan is the physical description of the ASIC design. In floorplanning we are mapping the logical description of the design to the physical description.
• Floorplanning is the process of placing blocks/macros in the chip/core area.
• Determine width and height of core and die.
• Determine location of predefined cell/macros.
• Determine I/O pin placement.
• Creating the Pad Ring for the Chip.
• Objective of floorplanning are to minimize the area and delay.

Placement

• Placement is the process of placing standard cells in the design. The tool determines the location of each standard cell on the die. The tool places these cells based on the algorithms which it uses internally.
• Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design. Placement also determines the routability of your design.
• Placement will be driven by different criteria like timing driven, congestion driven, power optimization.
• Objective of placement is to optimize the area, timing, power and minimal timing DRCs and minimal cell and pin density.
• The placement should be routable.

Clock Tree Synthesis (CTS)

• Clock Tree Synthesis (CTS) is a process which make sure that the clock signals distributed uniformly to all sequential elements in a design.
• CTS is the process of insertion of buffers or inverters along the clock paths of design in order to achieve minimum skew.
• Objective of CTS to meet clock tree design rule constraints such as maximum transition, maximum load capacitance and maximum fanout and to meet clock tree targets such as minimum skew and minimum insertion delay.

Routing

• Routing is the stage after CTS ,it is a process determines the precise paths for interconnections.
• Routing is nothing but connecting the various blocks in the chip with one an other.
• After CTS, we have information of all the placed cells, blockages, clock tree buffers/inverters and I/O pins. This information is important for tool to complete all the connections defined in netlist.
• In routing stage, metal and vias are used to create the electrical connection in layout defined by logical connections present in netlist.
• Objective of routing to meet the timing constraints, no LVS errors, no DRC errors and minimize the total wire length.
• There are many stages in routing process: a)Global routing b)Track assignment c)Detailed routing d) search and repair.

VLSI Physical Design & Verification and Signoff

• After routing stage your layout is ready. In this stage we have to perform signoff checks for example physical verification check, timing analysis, logical equivalence checking.
• We perform physical verification checks such as Layout Vs schematic (LVS) and Design Rule check (DRC) and Electrical Rule Check(ERC) and antenna check.
• Equivalence check will compare the netlist we started out with (pre-layout/synthesis netlist) to the netlist given by the tool after PnR(post layout netlist).
• DRC verifies whether the given layout satisfies the design rules provided by the fabrication team. DRC checks are nothing but physical checks of spacing rules between metals, minimum width rules, via rules etc.
• LVS is a major check in the physical verification stage. Layout is compared with the schematic for verifying whether their functionally match or not. If match, then the LVS reports clean.

All the input files are included in the VLSI Physical Design Process.

This section of the  article gives you the information on Physical Design (PD) which is a part of the ASIC/VLSI design flow in the semiconductor industry. In this article, we will see all the input files that are involved in the Physical Design process.

List of input files

There are several files that we pass as inputs to various steps of Physical Design. All the files and processes are mainly related to the Synopsys IC Compiler II tool.

Here is the list of the files required for Physical Design flow:

• Netlist
• SDC (Synopsys Design Constraint)
• .lib file (Library Timing File)
• .lef file (Library Exchange Format)
• .tf (Technology file)
• TLU+ file
• Scan def file
• MMMC (Multi-Mode Multi Corner)
• UPF file (Power Intent File)
• Don’t touch and Don’t use

A. RTL Netlist File (.v or .sv or .vhd)

It contains the connectivity information of gates, RTL file is converted into a technology-dependent gate-level netlist through the process of synthesis.

It contains:

• Logic gates.
• Flip flops.
• Interconnection details.
• Standard cells and macros information like name and drive strengths.

This is an important file and is required at every step of the physical design process. It is given by the synthesis team. It has the extension of .v file.

B. Synopsys Design Constraints File (.sdc)

This file is Synopsys Design Constraints. In this file, the synthesis team writes the timing constraints to meet the timing parameter.

It contains:

• Create clock definition (Source clock).
• Generated clock definition (Any generated clock from the source clock or another generated clock).
• Input/output delay
• Min/max delay
• Max transition, max capacitance, max fanout
• Clock latency, clock uncertainty.

It also contains clock exceptions like:

• Multi-cycle path
• Half cycle path
• Disable time arc
• Case analysis
• False path

We will look in detail for all the clock exceptions in another article. This file is saved with the .sdc extension. This is written in TCL.

C. Liberty Timing File (.lib)

It contains timing information of standard cells, soft macros, and hard macros. It contains Functionality information of standard cells and soft macros. Timing information like cell delay setup, hold, recovery, and removal are present.

The file contains units for time, voltage, leakage power, capacitive load, slew rate, and rise and fall time. Design rules like max tran, max cap, max fanout, min cap are present

Cell-specific information related to cells:

• Area of cell
• Power of cell
• Capacitance
• For each pin direction and their capacitance.

This file is provided by the vendor of the tool. This file is saved with a .lib extension.

D. Library Exchange File (.lef)

It contains physical information on standard cells, macros, and pads.

The information it contains is:

• Information about pin line pin name, space between pins, the direction of the pin, location of the pin, a layer of pins, height, and width of the pin, and cell.
• Contains height of standard cell row.
• Macro information like cell name, size, dimensions, layout, blockages, and capacitance are defined.

This file is provided by the tool vendor and is saved with the .lef extension.

E. Technology File (.tf)

It is a technology file that contains information about the number of metal layers and vias and their name and conventions.

Also, it contains the design rule for the metal layers:

• Width of each metal layer.
• Distance between two metal layers.

This is the file in ASCII format and saved with the .tf extension in Synopsys and contains the following things:

• Metal layer name.
• Type of metal.
• Resistance and capacitance of metal per unit area.
• Pitch between two layers.
• Spacing between metal layers.
• Unit, precision, color, and pattern of metal layer and via.
• Maximum current density is also present in the tech file.

This file is given by the foundry.

F.  Timing Library Update Plus File (TLU+)

This file contains:

• It is a table containing wire caps at different net lengths and spacing.
• Contains RC coefficient for a specific technology. R, C parasitics of metal per unit length.
• Extracted R, C parasitics of metal per unit length.

To load the TLU+ we need to load three files:

• TLU+
• Min TLU+
• Max TLU+

G. Scan DEF File (.def)

Contains scan chain information of the design DFT team creates the Scan DEF and gives as input to the PD team. This file is important to ease the process of connectivity in the routing stage. The scan chains are used to capture the internal state of the circuit, which can then be output for analysis and testing. DFT scan is an essential part of modern IC design, as it enables comprehensive testing of the circuit to ensure that it meets its specifications and is free of defects.

What are scan chains: Scan chains are the elements in scan-based designs that are used to shift-in and shift-out test data. A scan chain is formed by a number of flops connected back to back in a chain with the output of one flop connected to another. The input of first flop is connected to the input pin of the chip (called scan-in) from where scan data is fed. The output of the last flop is connected to the output pin of the chip (called scan-out) which is used to take the shifted data out. The figure below shows a scan chain.

Purpose of scan chains: As said above, scan chains are inserted into designs to shift the test data into the chip and out of the chip. This is done in order to make every point in the chip controllable and observable as discussed below.

How normal flop is transformed into a scan flop: The flops in the design have to be modified in order to be put in the scan chains. To do so, the normal input (D) of the flip-flop has to be multiplexed with the scan input. A signal called scan-enable is used to control which input will propagate to the output.

If scan-enable = 0, data at D pin of the flop will propagate to Q at the next active edge

If scan-enable= 1, data present at scan-in input will propagate to Q at the next active edge

Scan terminology: Before we talk further, it will be useful to know some signals used in scan chains which are as follows:

• Scan-in: Input to the flop/scan-chain that is used to provide scan data into it
• Scan-out: Output from flop/scan-chain that provides the scanned data to the next flop/output
• Scan-enable: Input to the flop that controls whether scan_in data or functional data will propagate to output
• Purpose of testing using scan: Scan testing is carried out for various reasons, two most prominent of them are:

•  To test stuck-at faults in manufactured devices
•  To test the paths in the manufactured devices for delay; i.e. to test whether each path is working at functional frequency or not

How a scan chain functions: The fundamental goal of scan chains is to make each node in the circuit controllable and observable through limited number of patterns by providing a bypass path to each flip-flop. Basically, it follows these steps:

1.  Assert scan_enable (make it high) so as to enable (SI -> Q) path for each flop
2.  Keep shifting in the scan data until the intended values at intended nodes are reached
3.  De-assert scan_enable (for one pulse of clock in case of stuck-at testing and two or more cycles in case of transition testing) to enable D->Q path so that the combinational cloud output can be captured at the next clock edge.
4.  Again assert scan_enable and shift out the data through scan_out

How Chain length is decided: By chain length, we mean the number of flip-flops in a single scan chain. Larger the chain length, more the number of cycles required to shift the data in and out. However, considering the number of flops remains same, smaller chain length means more number of input/output ports is needed as scan_in and scan_out ports. As

                Number of ports required = 2 X Number of scan chains

Since for each scan chain, scan_in and scan_out port is needed. Also,

               Number of cycles required to run a pattern = Length of largest scan chain in design

Suppose, there are 10000 flops in the design and there are 6 ports available as input/output. This means we can make (6/2=) 3 chains. If we make scan chains of 9000, 100 and 900 flops, it will be inefficient as 9000 cycles will be required to shift the data in and out. We need to distribute flops in scan chains almost equally. If we make chain lengths as 3300, 3400 and 3300, the number of cycles required is 3400.

Keeping almost equal number of flops in each scan chain is referred to as chain balancing.

H. MMMC File in VLSI Physical Design

Multi-mode multi-corner file is used to generate different analysis views based on different delay corners. There are various library set files based on voltage and temperature values.

What it is exactly about is that an actual chip is going to work in different temperatures and voltage levels, and the chip behaves differently in such cases, so to simulate this effect in simulations we need variables that can be varied like process (SS, FF, SF, FS…), temperature (low temp — -40C, medium temp — 0C, and high temp — 125C), voltage called as PVT.

Generally, there are 216 corners in total. But, we test nearly 30–40 corners in the MMMC file.

We have to do timing analysis on all corners so that the chip can function properly. So, using all corners the run time is very high for approximately 30 to 40 corners taken for timing analysis.

I. Unified Power Format File (UPF) in VLSI Physical Design

The power intent file describes which power rails should be routed to individual blocks. It also contains information on multi-voltage domains/low power designs (voltage shifters always on Buffers Retention cells).

• UPF (Unified Power Format) — Synopsys
• CPF (Common Power Format) — Cadence

J. Don’t touch and Don’t Use

Suppose during Synthesis there is one NAND gate we want to retain this NAND gate throughout our design. Hence, we will use don’t touch nets

Don’t touch the NAND gate

If we don’t want to use some during physical flow we give don’t use files For example LUTs we are removing the don’t touch attribute on the LUTs only after the post-route stage.

These are files that will be used as inputs to the physical design stage of ASIC flow. Other files are generated immediately in a few steps and then they are used in other steps (For example, DEF file). But the files mentioned above are files that are given directly.

What is the significance of DEF file in VLSI Physical Design?

It is a Data Exchange File written in ASCII format which is used to transfer the design from one EDA tool to another EDA tool for further implementation. It was developed by Cadence Design System. For example IR analysis on PnR database or STA on PnR database we transfer the design database in form of a DEF file.

Hope this article for useful for you. If you have a question regarding any file in this article, feel free to ask in comments. If you want me to write an article on any particular topic drop it in the comments. If you liked this article, surely share the article with friends and family.

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