Advanced VLSI Design
VLSI Course Name
Advanced VLSI Design.
Duration of the Advanced VLSI Course
6 Months (26 Weeks) including Theory, practical/labs, exams and final project work
Course Instructor
Course Instructor Name: K.R. Mohan
Phone Number & WhatsApp Number: +91 9148129900
Class Hours: Every Saturday and Sunday from 9AM to 1PM IST.
Reference Text Book for Advanced VLSI Course
Himanshu Bhatnagar, “Advanced ASIC Chip Synthesis”, Second Edition, Kluwer Academic Publishers (2002)
Supplementary Text Books
- David Smith and Paul Franzon, “Verilog Styles for Synthesis of Digital Systems”, Prentice Hall (2000).
- Dirk Janser et al., “The Electronic Design Automation Handbook”, Kluwer Academic Publishers (2003).
- Sachin Sapatnekar, “Timing”, Kluwer Academic Publishers (2004).
- Farzad Nekoogar, “Timing Verification”, Prentice Hall (1999).
- Cadence online documentation (cdsdoc)
- Synopsys online documentation
Advanced VLSI Course – Course Description
Advanced VLSI course introduces automated design tools, required for netlist synthesis, place & route and timing verification. Other advanced topics related to the design automation flow will be covered as time permits. Students will design a standard cell library for their project. Tools from both Synopsys Inc. and Cadence Design Systems will be introduced in this course.
VLSI Course Grading
The distribution of weights is as follows A pass mark of 70% or above is required to issue the course completion certificate
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1. Standard Cell Library Development
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20%
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2. Project Coding
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20%
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3. Project Implementation
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40%
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4. Exam (optional). Grade will be distributed evenly between above categories, if no exam is given.
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20%
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Tentative VLSI Course Outline
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Topics
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Timeline
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1. Standard Cell Library Development
Topics include: Layout (GDS II), Abstract Generation (LEF), Verilog, Circuit Extraction (Space), Circuit Simulation (Spice, TLF), Timing arcs and constraints, IO cells.
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3 classes
Assignment: 3 weeks
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2. Verilog
Synthesizable Verilog, basic constructs, simulators, test benches, combination and sequential constructs, state machines, datapath elements, FIFOs, multiple clock domain design.
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6 classes
Assignment: 4 weeks
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3. Synthesis, Place & Route
Synthesis tools, synthesis techniques, timing verification, floorplanning, power grid design, clock insertion, scan insertion, place & route.
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Remainder of classes
Assignments: Remainder of classes
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University Of Maryland Reference: http://www.cs.umbc.edu/~cpatel2/
