UPF ( Unified Power Format) in the Logic Synthesis Flow of VLSI Design & Verification

UPF is an acronym for Unified Power Format which is an IEEE standard for specifying power intent. In this article let’s understand the UPF files and tool flow and also we will learn about writing an UPF for a given power requirement in a design.

Understanding the Landscape

As semiconductor technology advances, chip complexity continues to escalate, leading to an exponential rise in power consumption. Efficiently managing power distribution and consumption is no longer a luxury but a necessity. This is where UPF steps in – a standardized format that acts as a common language between the design and implementation stages. It seamlessly integrates power intent into the design, ensuring optimal power management strategies are carried forward to the manufacturing phase.

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The Pillars of UPF

UPF offers a comprehensive set of features that enable designers to effectively manage power intent throughout the design process, ensuring efficient power consumption and optimization. Here’s a detailed breakdown of the key pillars of UPF:

1. Power Domains and Hierarchies:

Power domains are distinct regions within a chip that have separate power and ground networks. They allow different sections of the design to operate at varying power levels, optimizing power consumption. UPF provides a hierarchical structure for defining power domains and their relationships. This hierarchy can mirror the chip’s physical hierarchy or be customized to match the functional organization of the design.

• Domain Definitions: Designers can define power domains with their associated power and ground pins. These definitions are vital for understanding power network requirements and interactions.
• Hierarchy: UPF supports a hierarchical representation of power domains, enabling designers to organize power intent according to the design’s functional blocks and sub-blocks.

2. Power States and Modes:

Modern chips often operate in multiple power modes or states to balance performance and power consumption. UPF allows designers to specify these power modes, defining how the design transitions between them.

• Power Modes: UPF enables designers to describe various power modes, such as active mode, sleep mode, or standby mode. Each mode has its own power consumption characteristics.
• State Transitions: Designers can define conditions for transitioning between power states, ensuring smooth shifts in power modes based on factors like workload or user inputs.

3. Voltage and Power Area:

Voltage and power area definitions in UPF are crucial for managing power and performance trade-offs. Different blocks within a design might operate at distinct voltage levels to achieve the right balance between performance and energy efficiency.

• Voltage Definitions: Designers can define voltage domains and their associated voltage levels. This allows for adaptive voltage scaling, where voltage levels can be adjusted based on workload.
• Power-Aware Synthesis: UPF’s voltage and power area definitions influence the synthesis process, helping the tools optimize the design’s performance and power consumption.

4. Isolation and Retention Strategies:

During low-power modes, certain blocks may need to be isolated to prevent unwanted interactions or leakage power. UPF facilitates the definition of isolation and retention strategies for power domains.

• Isolation Cells: UPF allows designers to specify isolation cells that are inserted between power domains to prevent unintended interactions during power transitions.
• Retention: Designers can define which state each flip-flop should retain during low-power modes, ensuring critical data isn’t lost.

5. Interface with EDA Tools:

UPF isn’t just a theoretical framework; it seamlessly integrates with Electronic Design Automation (EDA) tools to ensure that power intent is consistently carried forward throughout the design process.

• Synthesis: UPF guides the synthesis tools to optimize the design while adhering to the specified power intent, voltage levels, and power modes.
• Place and Route: During place and route, UPF helps ensure that power network connectivity, isolation cells, and other power-related features are accurately implemented.

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Why UPF Matters ?

UPF matters profoundly in the field of VLSI design due to its pivotal role in addressing the pressing challenges of power management in complex integrated circuits. Here’s a comprehensive breakdown of why UPF holds such significance:

1. Power Efficiency and Energy Conservation:

With the ever-increasing demand for high-performance electronic devices, power consumption has become a critical concern. UPF enables systematic power management strategies that result in significant energy savings. By defining power domains, states, and modes, designers can dynamically adjust the power consumption of different parts of a chip based on workload, ensuring that power is utilized efficiently without compromising performance.

2. Automated Power Management:

The complexity of modern VLSI designs makes manual power management not only labor-intensive but error-prone. UPF automates the process by providing a standardized framework for specifying power intent. Designers can declare power-saving measures, such as power domains that can be shut down when not in use, or retention strategies that preserve critical data during low-power modes. This automation not only reduces the chance of human error but also streamlines the design process.

3. Industry Standardization and Collaboration:

UPF serves as a universal language for expressing power intent, facilitating seamless communication between designers, tool vendors, and semiconductor manufacturers. This standardization fosters collaboration and interoperability across different design stages and various EDA tools. It ensures that power intent is accurately conveyed throughout the design flow, from synthesis to implementation, leading to consistent and reliable power management.

4. Optimal Power-State Transitions:

UPF’s capability to define various power states and modes allows designers to orchestrate smooth transitions between them. This feature is particularly beneficial in scenarios where a design needs to switch between active, idle, or sleep modes. The ability to transition efficiently between power states minimizes energy wastage and enhances the overall power efficiency of the system.

5. Fine-Grained Control:

UPF empowers designers with fine-grained control over power domains, voltage levels, and power states. This is crucial for achieving a balance between performance and energy efficiency. Different blocks within a chip may require varying levels of power, and UPF enables designers to tailor power strategies to match the specific requirements of each block.

6. Green Computing and Environmental Impact:

In an era of heightened environmental awareness, power efficiency has become a key consideration in electronics design. UPF aligns with the principles of green computing by enabling the creation of energy-efficient chips with reduced power consumption and heat dissipation. This not only results in cost savings for end-users but also contributes to the reduction of carbon emissions and the overall environmental impact of technology.

7. Future Innovations and AI Integration:

As VLSI design continues to advance, UPF is poised to play a crucial role in harnessing the power of Artificial Intelligence for optimized power management. By incorporating AI-driven optimization techniques, UPF could further enhance power efficiency by dynamically adapting power strategies based on real-time data and workload patterns.

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UPF Flow in VLSI Design

RTL languages like VHDL and System Verilog don’t include the notion of power intent, just logic functionality, so something needed to be added for power intent.

Here’s an EDA tool flow showing where power intent files are used during design, verification and even implementation:

What’s inside a UPF file ?

Power intent is defined using an extension of the Tool Command Language (Tcl) and has the following components:

• Power Domains
• Power Supply Network
• Power State Table
• Isolation Strategies
• Retention Strategies
• Level Shifter Strategies
• Repeater Strategies

Who Creates UPF Files?

IP vendors supply RTL code, and constraint UPF file, then the design team adds a configuration UPF file for the specific context. Implementation-specific UPF files are also added along the way, so the EDA tool flow becomes:

How About Using Hierarchy ?

UPF supports both flat and hierarchical descriptions, and in general it’s recommended to align power domains with your logic hierarchy to keep life simple. If you choose to implement your design from the bottom-up, then ports need to be added in your UPF descriptions.

In a traditional bottom-up methodology an engineer would read all of the UPF files, then start manually editing each UPF file to ready them for merging into a top file. The UPF top-level file would be manually created, with care made to verify that proper syntax was typed. The power rules would also be verified before and after promotion.

Here’s a diagram showing a simple chip design example with four instances, named A, B, C, D; and at the top-level you can describe this with either hierarchy (left side), or as a flat design (right side):

In the example on the left, there are five UPF files organized in a hierarchy. On the right, there’s only one UPF file in a simpler setup. Changing between using UPF hierarchy or a flat structure is like moving up or down and involves detailed editing using a tool called TCL. You could do these edits by hand, hoping they’re all right, or you could use a special software tool designed for this job.

When you go from a single, flat UPF file to a collection of UPF files arranged hierarchically, it’s called moving down, and again, you have to edit things manually. If any changes are made to the RTL code during this process, it means more editing in the UPF files.

Example of a Design and how UPF Intent is Described for it (Credits – VLSITUTORIALS )

Consider the design shown below:

Given Power Intent:

There are primarily 3 power domains –

•  Logic inside aon_wrapper [but not inside aon_pgd_wrapper] is always-on.

•  Logic inside pgd_wrapper can be power gated.

•  Logic inside aon_pgd_wrapper can be power gated but won’t be power gated when pgd_wrapper is powered ON.

There are two voltage domains –

•  The supply voltage to logic inside aon_wrapper [but not inside aon_pgd_wrapper] and logic inside pgd_wrapper is 0.9V.

•  The supply voltage to logic inside aon_pgd_wrapper is 1.1V.

There are two registers – reg A and reg B. The state of reg A needs to be retained in power gated state.

There are six signals sig1-sig6 coming to and from different logic as shown in Figure1. After writing the UPF for the given power intent, the design gets modified into below Figure:

create_power_domain pd_top -include_scope
create_power_domain pd_aon -elements {aon_wrapper}
create_power_domain pd_gated -elements {pgd_wrapper}
create_power_domain pd_gated_aon -elements {{aon_wrapper/aon_pgd_wrapper}}

# Create Supply Ports

create_supply_port VCCL -direction in -domain pd_top
create_supply_port VCCH -direction in -domain pd_top
create_supply_port GND -direction in -domain pd_top

# Create Supply Nets

create_supply_net VCCL -domain pd_top
create_supply_net VCCH -domain pd_top
create_supply_net GND -domain pd_top

create_supply_net VCCL -domain pd_aon -reuse
create_supply_net GND -domain pd_aon -reuse

create_supply_net VCCH -domain pd_gated_aon –reuse
create_supply_net VCCH_gated -domain pd_gated_aon
create_supply_net GND -domain pd_gated_aon -reuse

create_supply_net VCCL -domain pd_gated -reuse
create_supply_net VCCL_gated -domain pd_gated
create_supply_net GND -domain pd_gated -reuse

# Connect Supply Nets with corresponding Ports

connect_supply_net VCCL -ports VCCL
connect_supply_net VCCH -ports VCCH
connect_supply_net GND -ports GND

# Establish Connections

set_domain_supply_net pd_top -primary_power_net VCCL -primary_ground_net GND
set_domain_supply_net pd_aon -primary_power_net VCCL -primary_ground_net GND
set_domain_supply_net pd_gated_aon -primary_power_net VCCH_gated -primary_ground_net GND
set_domain_supply_net pd_gated -primary_power_net VCCL_gated -primary_ground_net GND

# Shut-Down Logic for pgd_wrapper & aon_pgd_wrapper

create_power_switch sw_pgd_wrapper \
-domain pd_gated \
-input_supply_port “sw_VCCL VCCL ” \
-output_supply_port “sw_VCCL_gated VCCL_gated” \
-control_port “sw_pgd_en aon_wrapper/pmu/pgd_en” \
-on_state “SW_PGD_ON sw_VCCL {!sw_pgd_en}”

create_power_switch sw_aon_pgd_wrapper \
-domain pd_gated_aon \
-input_supply_port “sw_VCCH VCCH ” \
-output_supply_port “sw_VCCH_gated VCCH_gated” \
-control_port “sw_aon_pgd_en aon_wrapper/pmu/aon_pgd_en” \
-on_state “SW_AONPGD_ON sw_VCCH {!sw_aon_pgd_en}”

# Isolation strategy

set_isolation isol_clamp1_sig_from_pgd \
-domain pd_gated \
-isolation_power_net VCCL \
-isolation_ground_net GND \
-clamp_value 1 \
-elements {pgd_wrapper/sig2}

set_isolation_control isol_clamp1_sig_from_pgd \
-domain pd_gated \
-isolation_signal aon_wrapper/pmu/isol_pgd_en \
-isolation_sense low \
-location parent

set_isolation isol_clamp0_sig_from_pgd \
-domain pd_gated \
-isolation_power_net VCCL \
-isolation_ground_net GND \
-clamp_value 0 \
-elements {pgd_wrapper/sig4}

set_isolation_control isol_clamp0_sig_from_pgd \
-domain pd_gated \
-isolation_signal aon_wrapper/pmu/isol_pgd_en \
-isolation_sense low \
-location parent

set_isolation isol_sig_from_aonpgd \
-domain pd_gated_aon \
-isolation_power_net VCCH \
-isolation_ground_net GND \
-clamp_value 1 \
-elements {aon_wrapper/aon_pgd_wrapper/sig5}

set_isolation_control isol_sig_from_aonpgd \
-domain pd_gated_aon \
-isolation_signal aon_wrapper/pmu/isol_aonpgd_en \
-isolation_sense low \
-location parent

# Level Shifter strategy

set_level_shifter LtoH_sig_to_aonpgd \
-domain pd_gated_aon \
-applies_to inputs \
-rule low_to_high \
-location self

set_level_shifter HtoL_sig_from_aonpgd \
-domain pd_gated_aon \
-applies_to outputs \
-rule high_to_low \
-location self

# Retention strategy

set_retention pgd_retain \
-domain pd_gated \
-retention_power_net VCCL \
-retention_ground_net GND \
-elements {pgd_wrapper/regA}

set_retention_control pgd_retain \
-domain pd_gated \
-save_signal {aon_wrapper/pmu/ret_en high} \
-restore_signal {aon_wrapper/pmu/ret_en low}

# Create Power State Table

add_port_state VDDH \
-state {HighVoltage 1.1}
add_port_state VDDL \
-state {LowVoltage 0.9}
add_port_state sw_aon_pgd_wrapper/sw_VCCH_gated \
-state {HighVoltage 1.1} \
-state {aonpgd_off off}
add_port_state sw_pgd_wrapper/sw_VCCL_gated \
-state {LowVoltage 0.9} \
-state {pgd_off off}

create_pst pwr_state_table \
-supplies {VCCH VCCL VDDH_gated VDDL_gated}

add_pst_state PRE_BOOT \
-pst pwr_state_table \
-state { HighVoltage LowVoltage aonpgd_off pgd_off}
add_pst_state AONPGD_ON \
-pst pwr_state_table \
-state { HighVoltage LowVoltage HighVoltage pgd_off}
add_pst_state PGD_ON \
-pst pwr_state_table \
-state { HighVoltage LowVoltage aonpgd_off LowVoltage}
add_pst_state ALL_ON \
-pst pwr_state_table \
-state { HighVoltage LowVoltage HighVoltage LowVoltage}

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Challenges and Future Prospects of UPF

While UPF has undoubtedly transformed power management in VLSI, challenges persist. These include:

1. Multi-Voltage Designs:

One of the primary challenges in power management is dealing with designs that incorporate multiple voltage domains. Different blocks or modules within a chip may require distinct voltage levels for optimal performance and energy efficiency. Coordinating the power transitions between these voltage domains while ensuring correct timing and signal integrity is a complex task that UPF needs to address effectively.

2. Power Domain Interactions:

Power domains within a chip often interact with each other during various operational modes. Managing these interactions, such as voltage scaling and state transitions, is a complex challenge. Incorrect handling can lead to issues like glitches, signal integrity problems, and increased power consumption. Designers need to carefully define UPF constructs to ensure smooth interactions and minimize unintended consequences.

3. Advanced Low-Power Techniques:

As low-power techniques continue to evolve, UPF must adapt to incorporate these advanced methodologies. Techniques like body-biasing, power gating, and dynamic voltage and frequency scaling (DVFS) require precise control and coordination. Integrating these techniques into the UPF framework while maintaining backward compatibility poses a challenge, as these techniques might have intricate dependencies.

4. EDA Tool Support:

While UPF has gained widespread adoption, ensuring consistent support for all its features across various Electronic Design Automation (EDA) tools is not always straightforward. Different tools might interpret and implement UPF constructs differently, leading to discrepancies and potential design issues. Designers must navigate these tool-related challenges to achieve the desired power intent in their designs.

Looking ahead, the evolution of UPF will likely involve:

1. AI-Driven Power Optimization:

Artificial Intelligence and Machine Learning technologies are making significant strides in the semiconductor industry. Future UPF implementations might leverage AI algorithms to automatically optimize power management strategies. These algorithms could learn from historical design data, analyze complex interactions, and generate power intent that maximizes energy efficiency while meeting performance targets.

2. System-Level Power Management:

With the growing complexity of modern SoCs, power management is moving beyond individual blocks. Future UPF versions might extend their scope to encompass system-level power management, enabling efficient control of power domains across multiple chips, interfaces, and heterogeneous components. This would enhance overall energy savings and coordination.

3. Energy Harvesting Integration:

As energy harvesting technologies gain traction, UPF could potentially incorporate mechanisms to integrate harvested energy sources seamlessly into the power management framework. This could involve dynamically adjusting power states based on available harvested energy, enabling autonomous and energy-efficient devices in applications like IoT.

4. Cross-Disciplinary Collaboration:

The advancement of UPF will likely involve collaboration with adjacent fields such as battery technology, system architecture, and thermal management. Efficient power management requires a holistic approach, and future UPF versions could integrate feedback from these disciplines to optimize power decisions that factor in thermal constraints, battery life, and system-level performance.

Unified Power Format stands as a cornerstone of modern VLSI design. Its ability to harmonize power intent across the design flow, coupled with the promise of energy-efficient chips, makes UPF an indispensable tool in the arsenal of VLSI engineers. Let’s embrace UPF and power a future where high performance meets sustainable computing.