Output fall delay and rise delay - VLSI Courses

Liberty Timing File (.lib) in VLSI Design & Verification Flow

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What is Liberty Format ?

Lib file is a short form of Liberty Timing file. Liberty syntax is followed to write a .lib file. LIB file is an ASCII representation of timing and power parameter associated with cells inside the standard cell library of a particular technology node.  Liberty format is an industry standard format used to describe library cells of a particular technology. A cell could be a standard cell, IO Buffer, complex IP etc. Library cell description contains a lot of information like timing information, power estimation, other several attributes like area, functionality, operating condition etc. Speaking more technically, liberty format is a format to represent timing and power properties of black boxes (which we cant descend into). Liberty is an ASCII format, usually represented in a text file with extension “.lib“. In this section, we will discuss timing aspects (delay and transition times) related to liberty forma

Structure of the Liberty Format

The information inside the Lib file can be divided into two main parts, in the first part, it contains some information which is common for all the standard cells. To understand it better have a look in the following snapshot of the Lib file.

lib_file_comman

Figure: This information of .lib file is common for all the standard cells

The common part of Lib file contains:

  1. Library name and technology name
  2. Units (of time, power, voltage, current, resistance and capacitance)
  3. Value of operating condition ( process, voltage and temperature) – Max, Min and Typical

Based on operating conditions there are three different lib files for Max, Min and Typical corners. In the second part of Lib file, it contains cell-specific information for each cell. The part of Lib file which contains cell-specific information is shown below.

Lib_cell_part
Figure: Part of Lib file which contains cell-specific information

Cell-specific information in Lib file is mainly:

  1. Cell name
  2. PG Pin name
  3. Area of cell
  4. Leakage power in respect of input pins logic state

Pins Details:

    1. Pin name
    2. Pin direction
    3. Internal power
    4. Capacitance
    5. Raise capacitance
    6. Fall Capacitance
    7. Fanout load

A snapshot of Lib file for the pin part is given below.

Pin part of the Lib file
Figure: Pin part of the Lib file
Timing and power parameter of a cell is obtained by simulating the cell in a variety of operating conditions and data are represented in the Lib file. There are two main techniques to characterize a cell and generated the Lib file.
  • CCS (Composite Current Source)
  • NLDM (Non-Linear Delay Model)
In CCS technique current source is used whereas in NLDM technique voltage source is used to model and derive the Lib parameters. Based on CCS and NLDM technique used for characterizing the cell, we call the corresponding Lib file is CCS Lib file and NLDM Lib file. Since CCS technique is having more controlling parameters as compare to NLDM technique, So CCS Lib file is more accurate. NLDM Lib file has lesser run time mean fast run compare to CCS Lib and also the size of the NLDM file is lesser than that of CCS Lib file.

How is Liberty File Populated with Data ?

The cells represented through liberty files are first simulated under a variety of conditions representative of actual design conditions that the cell may be exposed to. This process is known as characterization of library cells. As a very simple example, the delay of an inverter depends upon the input transition time and output load capacitance seen by it. The inverter will be characterized for a range of input transitions and output load capacitances. This characterization data, will then, be put into liberty in the form of a look-up table representing delay values at different transition times and load values.
To understand the different constructs related to timing in liberty file, let us take example of inverter. Rising transition at the input of inverter produces falling transition at the output of inverter and vice-versa. Hence there are two types of delay :
  1. Rise delay : It is the propagation delay between output and input when output changes from 0 to 1.
  2. Output fall delay : It is the propagation delay between output and input when output is changing from 1 to 0.
In the real world, signal does not change its state from 0 to 1 or 1 to 0 abruptly. It takes some time to change its state. Hence, delay is measured based upon the threshold points. Threshold points in the liberty file are specified as below:
# threshold point of input falling edge
input_threshold_pct_fall : 50.0 ;# threshold point of input rising edge
input_threshold_pct_rise : 50.0 ;#threshold point of output falling edge
output_threshold_pct_fall : 50.0 ;#threshold point of output rising edge
output_threshold_pct_rise : 50.0 ;
NOTE : these values are in percentage. e.g. If vdd is 5v then all of the above values will be 2.5.
So, Output rise delay is time difference between output_threshold_pct_rise and input_threshold_pct fall. Similarly Output fall delay is time difference between output_threshold_pct_fall and input_threshold_pct_rise.
Output fall delay and rise delay
Figure: Output fall delay (Tfall) and rise delay (Trise)
Transition time : Time it takes for a signal to changes its state from one level to another level. Transition time is represented in terms of slew in liberty. Actually slew is inversely proportional to transition time. More the transition time, lesser is the slew rate and vice-versa. As we know that
voltage transition at the output is :

V = Vdd * [ 1 – e^ ( -t/(RC ) ) ]

As Voltage equation is exponential, the voltage waveform is asymptotic at ends It is difficult to determine the exact start and end point of transition hence transition time is defined in terms of threshold values as follow :
# lower threshold point for falling  edge
slew_lower_threshold_pct_fall  : 30;
# upper threshold point for falling  edge
slew_upper_threshold_pct_fall : 30;
# lower threshold point for rising  edge
slew_lower_threshold_pct_rise : 70;
# upper threshold point for rising  edge
slew_upper_threshold_pct_rise : 70;
rise_fall
Figure: Rise Slew and Fall Slew

Difference Between PDK (Process Development Kit) and DDK (Digital Design Kit)

PDK is for Analog Designers  or for Custom IC Layout Designers(Mainly to use with Cadence Virtuoso Tools or Synopsys Custom Compiler).
Standard Cell Library is for Digital Designers  or for Digital Design & Verification Flow (To use with tools such as Synopsys Design Compiler/Fusion Compiler, Cadence Genus etc.)

PDK is nothing but Process Development Kit. PDK will have Pcell’s, transistor models etc.
DDK is Digital Design Kit. Standard Cell Library contains all the primitive cells that are requested by the Physical Design Engineers.

Standard Cell Libraries: are the basic building block of any advance digital IC, they contain all the combinational & sequential digital & mixed signal cells which will be used for the creation of SOC or ASIC. These cells will be arranged & connected in an orderly & meaningful pattern by using synthesis tools such as Fusion Compiler or Design/RTL Compiler(Synopsys), later on these cells along with other hard & soft marcos are used to create complete SOC. Normally people term .lib as Standard cell but they are wrong because Standard lib contains GDS2, DEF, LEF, (timing, power area & cap info of cells in .lib syntax), milkyway data base (FRAM, CEL etc.), CDL & RC-info in extracted netlist, noise info in celtic or ccsn format, voltage storm views etc. These  are used at different stages of ASIC design by different EDA tools.

PDK: its definition varies from company to company what I know is PDK (Process Development Kit) contains info about the process for which the SOC or ASIC is been targeted, they are been even used to create even Standard cells, Memories, I/O’s & Analog portion typically they contains DRC, DFM, Antenna, LVS & extraction rule decks, along with SPICE models which are used during simulations. All the DRC & DFM info is been used to create P-cells (Cadence nomenclature) which are used in Cadence Virtuoso.

Video – PDK/DDK in VLSI Physical Design

Video – What is Standard Cell Characterization & How Liberty File .lib is Created?

 

References

Standard Library Cells Development  –  VTVT University

Timing Library LVF Validation For Production Design Flows

 

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